Interrupts
This tutorial briefly explains what are interrupts, how are they managed, and with few examples in C.
An interrupt is a message or a signal raised by a device, such as mouse, clock, keyboard, to the processor to pause its current work and give some attention towards it. These devices generate interrupts when they have data ready to be read or ready to be taken in. For example, you press a key on your keyboard, the keyboard sends the signal to the keyboard controller and the keyboard controller will fire an interrupt (IRQ 1) to the CPU to tell that a key has been pressed. IBM PC/AT computers with a 286 or a later processor have 2 chips which will manage these device interrupts. These chips are known as Programmable Interrupt Controllers(PIC).There are two chips namely Master IRQ Controller and the Slave IRQ Controller. The Slave IRQ Controller is connected to the Master IRQ Controller by IRQ 2. The PCI manages IRQ’s equally; 0-7 IRQ’s are managed by the Master IRQ Controller, and 8-15 IRQ's are managed by the Slave IRQ Controller.When an interrupt is raised ,the processor would look at the table in the memory called IDT which is setup by the Operating System and then the IDT would call the appropriated handler.
There are 256 interrupts, 0-16 raised by the hardware, 32(0-31) interrupts for processor exceptions, and software interrupts.The CPU checks the PCI pins for a interrupt every time after a machine instruction was processed .When a CPU notifies that an interrupt is fired ,it saves its current state to the stack and jumps to the handler located in the IDT and the rest will be handled by the OS. Then the processor will pop its previous state from the stack.
NMI- Non-maskable interrupts
A non-maskable interrupt (NMI) is a computer processor interrupt that cannot be ignored by standard interrupt masking techniques in the system. It is typically used to signal attention for non-recoverable hardware errors.
CLI and STI Instruction
STI and CLI are assembly instructions which stand for “set interrupt flag” and “clear interrupt flag”.These functions are used to set and clear the interrupt enable flag.The STI instruction is used to enable interrupts and CLI is used to disable the interrupts.
Examples in C(GCC) using inline assembly:
void enable_interrupts ()
{
__asm__ (“sti”);//Enables the interrupts , set the interrupt flag
}
void disable_interrupts ()
{
__asm__ (“cli”);//Disables interrupts ,clears the interrupt flag
}
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Interrupt Requests List: Shows all the interrupts with its respective device
IRQ DEVICE
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Interrupts Map
0-31 Protected Mode Processor Exceptions (Reserved by Intel Processors)
8-15 Default mapping of IRQ 0-7 by the BIOS at bootstrap
70h-78h Default mapping of IRQ 8-15 by the BIOS at bootstrap
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PIC Ports
20h & 21h Master PIC
A0h & A1h Slave PIC
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Glossary:
There are 256 interrupts, 0-16 raised by the hardware, 32(0-31) interrupts for processor exceptions, and software interrupts.The CPU checks the PCI pins for a interrupt every time after a machine instruction was processed .When a CPU notifies that an interrupt is fired ,it saves its current state to the stack and jumps to the handler located in the IDT and the rest will be handled by the OS. Then the processor will pop its previous state from the stack.
NMI- Non-maskable interrupts
A non-maskable interrupt (NMI) is a computer processor interrupt that cannot be ignored by standard interrupt masking techniques in the system. It is typically used to signal attention for non-recoverable hardware errors.
CLI and STI Instruction
STI and CLI are assembly instructions which stand for “set interrupt flag” and “clear interrupt flag”.These functions are used to set and clear the interrupt enable flag.The STI instruction is used to enable interrupts and CLI is used to disable the interrupts.
Examples in C(GCC) using inline assembly:
void enable_interrupts ()
{
__asm__ (“sti”);//Enables the interrupts , set the interrupt flag
}
void disable_interrupts ()
{
__asm__ (“cli”);//Disables interrupts ,clears the interrupt flag
}
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Interrupt Requests List: Shows all the interrupts with its respective device
IRQ DEVICE
- IRQ 0 System Timer(PIT ,etc)
- IRQ 1 Keyboard
- IRQ 2 Slave PCI Controller
- IRQ 3 Serial Ports (COM 2 and COM 4)
- IRQ 4 Serial Ports(COM 1 and COM 3)
- IRQ 5 Sound cards
- IRQ 6 Floppy disk controller
- IRQ 7 First Parallel Port
- IRQ 8 Real-time clock
- IRQ 9 Open interrupt
- IRQ 10 Open interrupt
- IRQ 11 Open interrupt
- IRQ 12 PS/2 mouse
- IRQ 13 Floating Point Unit/Co-processor
- IRQ 14 Primary Integrated Drive Electronics (IDE) channel
- IRQ 15 Secondary IDE channel
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Interrupts Map
0-31 Protected Mode Processor Exceptions (Reserved by Intel Processors)
8-15 Default mapping of IRQ 0-7 by the BIOS at bootstrap
70h-78h Default mapping of IRQ 8-15 by the BIOS at bootstrap
------------------------------------------------------------------------------------------------------------------------------
PIC Ports
20h & 21h Master PIC
A0h & A1h Slave PIC
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Glossary:
- IRQ Interrupt Request
- PIC Programmable Interrupt Controller
- IDT Interrupt descriptor table
- CLI Clear Interrupt Flag
- STI Set Interrupt Flag
- NMI Non-maskable Interrupts
- IDE Integrated Disk Electronics or Integrated Drive Electronics